HB56U232BA/SBA Series 2,097,152-word x 32-bit High Density Dynamic RAM Module ADE-203-721B (Z) Rev. 2.0 May. 26, 1997 Description The HB56U232BA/SBA is a 2M x 32 dynamic RAM module, mounted 4 pieces of 16-Mbit DRAM (HM5117805) sealed in SOJ package. The HB56U232BA/SBA offers Extended Data Out (EDO) Page Mode as a high speed access time. An outline of the HB56U232BA/SBA is 72-pin single in-line package. Therefore, the HB56U232BA/SBA makes high density mounting possible without surface mount technology. The HB56U232BA/SBA provides common data inputs and outputs. Decoupling capacitors are mounted on the module board. Features * 72-pin single in-line package Outline: 107.95 mm (Length) x 25.40 mm (Height) x 5.28 mm (Thickness) Lead pitch: 1.27 mm * Single 5 V (5%) supply * High speed Access time: tRAC = 50/60/70ns (max) * Low power dissipation Active mode: 2.31/2.10/1.89 W (max) Standby mode (TTL): 42 mW (max) (CMOS): 3.15 mW (max) (L-version) * EDO page mode capability * Refresh period 2048 refresh cycles: 32 ms 128 ms (L-version) * 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh * TTL compatible HB56U232BA/SBA Series Ordering Information Type No. Access time Package Contact pad HB56U232BA-5N HB56U232BA-6N HB56U232BA-7N 50 ns 60 ns 70 ns 72-pin SIP socket type Gold HB56U232BA-5NL HB56U232BA-6NL HB56U232BA-7NL 50 ns 60 ns 70 ns HB56U232SBA-5N HB56U232SBA-6N HB56U232SBA-7N 50 ns 60 ns 70 ns 72-pin SIP socket type Solder HB56U232SBA-5NL HB56U232SBA-6NL HB56U232SBA-7NL 50 ns 60 ns 70 ns 2 HB56U232BA/SBA Series Pin Arrangement 1Pin 36Pin 37Pin 72Pin Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 1 VSS 19 A10 37 NC 55 DQ11 2 DQ0 20 DQ4 38 NC 56 DQ27 3 DQ16 21 DQ20 39 VSS 57 DQ12 4 DQ1 22 DQ5 40 CAS0 58 DQ28 5 DQ17 23 DQ21 41 CAS2 59 VCC 6 DQ2 24 DQ6 42 CAS3 60 DQ29 7 DQ18 25 DQ22 43 CAS1 61 DQ13 8 DQ3 26 DQ7 44 RAS0 62 DQ30 9 DQ19 27 DQ23 45 NC 63 DQ14 10 VCC 28 A7 46 NC 64 DQ31 11 NC 29 NC 47 WE 65 DQ15 12 A0 30 VCC 48 NC 66 NC 13 A1 31 A8 49 DQ8 67 PD1 14 A2 32 A9 50 DQ24 68 PD2 15 A3 33 NC 51 DQ9 69 PD3 16 A4 34 RAS2 52 DQ25 70 PD4 17 A5 35 NC 53 DQ10 71 NC 18 A6 36 NC 54 DQ26 72 VSS 3 HB56U232BA/SBA Series Pin Description Pin name Function A0 to A10 Address inputs: Row address: A0 to A10 Column address: A0 to A9 Refresh address: A0 to A10 DQ0 to DQ31 Data-in/Data-out CAS0 to CAS3 Column address strobe RAS0, RAS2 Row address strobe WE Read/Write enable VCC Power supply VSS Ground PD1 to PD4 Presence detect pin NC No connection Presence Detect Pin Arrangement Function Pin No. Pin name 50 ns 60 ns 70 ns 67 PD1 NC NC NC 68 PD2 NC NC NC 69 PD3 VSS NC VSS 70 PD4 VSS NC NC 4 HB56U232BA/SBA Series Block Diagram RAS0 CAS0 CAS RAS 8 I/O0 to I/O7 D0 DQ0 to DQ7 OE CAS1 CAS RAS 8 I/O0 to I/O7 D1 DQ8 to DQ15 OE RAS2 CAS2 CAS RAS 8 I/O0 to I/O7 D2 DQ16 to DQ23 OE CAS3 CAS RAS 8 I/O0 to I/O7 D3 DQ24 to DQ31 OE VCC VSS D0 to D3 0.22 F x 9 pcs WE D0 to D3 D0 to D3 11 A0 to A10 D0 to D3 * D0 to D3: HM5117805 5 HB56U232BA/SBA Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT -1.0 to +7.0 V Supply voltage relative to VSS VCC -1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation Pt 4 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Recommended DC Operating Conditions (Ta = 0 to 70C) Parameter Symbol Min Typ Max Unit Supply voltage VSS 0 0 0 V VCC 4.75 5.0 5.25 V 1 Input high voltage VIH 2.4 -- 5.5 V 1 Input low voltage VIL -1.0 -- 0.8 V 1 Note: 6 1. All voltage referred to VSS . Note HB56U232BA/SBA Series DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes Operating current I CC1 -- 440 -- 400 -- 360 mA t RC = min 1, 2 Standby current I CC2 -- 8 -- 8 -- 8 mA TTL interface, RAS, CAS = VIH, Dout = High-Z -- 4 -- 4 -- 4 mA CMOS interface, RAS, CAS VC C - 0. 2 V, Dout = High-Z -- 0.6 -- 0.6 mA CMOS interface, RAS, CAS VC C - 0. 2 V, Dout = High-Z Standby current (L-version) I CC2 -- 0.6 RAS-only refresh current I CC3 -- 440 -- 400 -- 360 mA t RC = min 2 Standby current I CC5 -- 20 20 20 RAS = VIH, CAS = VIL, Dout = enable 1 CAS-before-RAS refresh current I CC6 -- 440 -- 400 -- 360 mA t RC = min EDO page mode current I CC7 -- 400 -- 360 -- 340 mA t HPC = min 1, 3 Battery backup current I CC10 (Standby with CBR refresh) (L-version) -- 2 2 2 mA CMOS interface, Dout = High-Z, CBR refresh: t RC = 62.5 s, t RAS 0.3 s 4 Input leakage current I LI -10 10 -10 10 -10 10 A 0 V Vin 5.5 V Output leakage current I LO -10 10 -10 10 -10 10 A 0 V Vout 5.5 V, Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = -2 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 2 mA -- -- -- -- mA Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L ( 0.2 V) while RAS = L ( 0.2 V). 7 HB56U232BA/SBA Series Capacitance (Ta = 25C, VCC = 5 V 5%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 -- 40 pF 1 Input capacitance (WE) CI2 -- 48 pF 1 Input capacitance (RAS) CI3 -- 29 pF 1 Input capacitance (CAS) CI4 -- 22 pF 1 I/O capacitance (DQ) CI/O -- 22 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 8 HB56U232BA/SBA Series AC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) *1, *2 , *18 Test Conditions * * * * * Input rise and fall times: 2 ns Input level: 0 V, 3.0V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, and Refresh Cycles (Common parameters) 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Random read or write cycle time t RC 84 -- 104 -- 124 -- ns RAS precharge time t RP 30 -- 40 -- 50 -- ns CAS precharge time t CP 7 -- 10 -- 13 -- ns RAS pulse width t RAS 50 10000 60 10000 70 10000 ns CAS pulse width t CAS 7 10000 10 10000 13 10000 ns Row address setup time t ASR 0 -- 0 -- 0 -- ns Row address hold time t RAH 7 -- 10 -- 10 -- ns Column address setup time t ASC 0 -- 0 -- 0 -- ns Column address hold time t CAH 7 -- 10 -- 13 -- ns RAS to CAS delay time t RCD 11 37 14 45 14 52 ns 3 RAS to column address delay time t RAD 9 25 12 30 12 35 ns 4 RAS hold time t RSH 10 -- 13 -- 13 -- ns CAS hold time t CSH 35 -- 40 -- 45 -- ns CAS to RAS precharge time t CRP 5 -- 5 -- 5 -- ns CAS delay time from Din 0 -- 0 -- 0 -- ns Transition time (rise and fall) t T 2 50 2 50 2 50 ns Refresh period (2,048 cycles) t REF -- 32 -- 32 -- 32 ms Refresh period (2,048 cycles) (L-version) t REF -- 128 -- 128 -- 128 ms t DZC Notes 5 9 HB56U232BA/SBA Series Read Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC -- 50 -- 60 -- 70 ns 6, 7 Access time from CAS t CAC -- 13 -- 15 -- 18 ns 7, 8, 15 Access time from address t AA -- 25 -- 30 -- 35 ns 7, 9, 15 Read command setup time t RCS 0 -- 0 -- 0 -- ns Read command hold time to t RCH CAS 0 -- 0 -- 0 -- ns Read command hold time from RAS 50 -- 60 -- 70 -- ns Read command hold time to t RRH RAS 5 -- 5 -- 5 -- ns Column address to RAS lead time t RAL 25 -- 30 -- 35 -- ns Column address to CAS lead time t CAL 15 -- 18 -- 23 -- ns CAS to output in low-Z t CLZ 0 -- 0 -- 0 -- ns Output data hold time t OH 3 -- 3 -- 3 -- ns 19 Output buffer turn-off time t OFF -- 13 -- 15 -- 15 ns 11, 19 CAS to Din delay time t CDD 13 -- 15 -- 18 -- ns Output data hold time from RAS t OHR 3 -- 3 -- 3 -- ns 19 Output buffer turn-off time to t OFR RAS -- 13 -- 15 -- 15 ns 19 Output buffer turn-off to WE t WEZ -- 13 -- 15 -- 15 ns WE to Din delay time t WED 13 -- 15 -- 18 -- ns RAS to Din delay time t RDD 13 -- 15 -- 18 -- ns 50 -- 60 -- 70 -- ns t RCHR RAS to next CAS delay time t RNCD 10 10 10 HB56U232BA/SBA Series Write Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 -- 0 -- 0 -- ns 12 Write command hold time t WCH 7 -- 10 -- 13 -- ns Write command pulse width t WP 7 -- 10 -- 10 -- ns Data-in setup time t DS 0 -- 0 -- 0 -- ns 13 Data-in hold time t DH 7 -- 10 -- 13 -- ns 13 Notes Refresh Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit CAS setup time (CBR refresh cycle) t CSR 5 -- 5 -- 5 -- ns CAS hold time (CBR refresh cycle) t CHR 7 -- 10 -- 10 -- ns WE setup time (CBR refresh cycle) t WRP 0 -- 0 -- 0 -- ns WE hold time (CBR refresh cycle) t WRH 7 -- 10 -- 10 -- ns RAS precharge to CAS hold t RPC time 5 -- 5 -- 5 -- ns EDO Page Mode Cycle 50 ns 60 ns 70 ns Parameter Symbol Min Max Min Max Min Max Unit Notes EDO page mode cycle time t HPC 20 -- 25 -- 30 -- ns 16 EDO page mode RAS pulse t RASP width -- 100000 -- 100000 -- 100000 ns 14 Access time from CAS precharge t CPA -- 28 -- 35 -- 40 ns 7, 15 RAS hold time from CAS precharge t CPRH 28 -- 35 -- 40 -- ns Output data hold time from CAS low t DOH 3 -- 3 -- 3 -- ns Read command hold time from CAS precharge t RCHC 28 -- 35 -- 40 -- ns 7, 15 11 HB56U232BA/SBA Series Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD tRCD (max) + tAA (max) - tCAC (max), then access time is controlled exclusively by t CAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 6. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 8. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 9. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 10. Either t RCH or tRRH must be satisfied for a read cycles. 11. t OFF (max) defines the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 12. Early write cycle only (tWCS tWCS (min)). 13. These parameters are referred to CAS leading edge in early write cycles. 14. t RASP defines RAS pulse width in EDO page mode cycles. 15. Access time is determined by the longest among t AA , t CAC and t CPA. 16. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. 17. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC / VSS line noise, which causes to degrade V IH min./ V IL max level. 18. All the V CC and VSS pins shall be supplied with the same voltages. 19. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH , and between t OFR and t OFF. 20. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 12 HB56U232BA/SBA Series Timing Waveforms*20 Read Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT CAS t RAD t ASR Address t RAH t RAL t ASC t CAL t CAH Column Row t RRH t RCHR t RCH t RCS WE t WED t DZC t CDD t RDD High-Z Din t CAC t OFF t OH t OFR t OHR t AA t RAC t CLZ t WEZ Dout Dout 13 HB56U232BA/SBA Series Early Write Cycle t RC t RP t RAS RAS t CSH t CRP t RCD t RSH t CAS tT CAS t ASR Address t RAH Row t ASC t CAH Column t WP t WCS t WCH WE t DS Din Dout t DH Din High-Z* * t WCS 14 t WCS (min) HB56U232BA/SBA Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP t RPC t CRP CAS t ASR Address t RAH Row t OFR t OFF High-Z ! Dout 15 HB56U232BA/SBA Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP RAS t CSR t CHR t RPC t CRP , t RPC tT CAS t CP t WRP t WRH t CP WE Address t OFR t OFF Dout 16 High-Z HB56U232BA/SBA Series Hidden Refresh Cycle t RC t RC t RP t RAS t RAS t RC t RP t RAS t RP RAS tT t RSH t CHR t CRP t RCD CAS t RAD t ASR t RAH Address t RAL t ASC Row t CAH Column t WRH t WRP t WRP tWRH t RRH t RCH , #* t RCS t RRH WE t WED t DZC t CDD t RDD High-Z Din t CAC t AA t WEZ t RAC t OFF t OH t CLZ Dout Dout t OFR t OHR 17 HB56U232BA/SBA Series EDO Page Mode Read Cycle t RP t RNCD t HPC t RASP RAS tT t CSH t CP t HPC t CAS CAS t HPC t CPRH t CP t t CRP RSH t CAS t RCHR t RCS t CP tCAS tCAS t RCHC t RCH t RCS t RRH t RCH WE tASR Address tRAH tASC Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CAL tASC t RAL t CAH t WED Column 4 t CAL t CAL tRDD tCDD tDZC High-Z Din tOFR tOHR tCPA !" tCPA tCPA tAA tCAC tAA tCAC tCAC tAA tWEZ tRAC Dout 18 t AA t CAC tDOH Dout 1 Dout 2 tOFF tOH tDOH Dout 3 Dout 4 HB56U232BA/SBA Series EDO Page Mode Early Write Cycle t RP t RASP RAS tT t CSH t RCD t CAS t CP t HPC t CAS t RSH t CAS t CP t CRP CAS t ASR t RAH Address Row t ASC t CAH t ASC tCAH t ASC t CAH Column 1 Column 2 Column N t WP t WP t WP t WCS t WCH t WCS t WCH t WCS t WCH WE t DS Din Dout t DH Din 1 t DS t DH Din 2 t DS t DH Din N High-Z* * t WCS t WCS (min) 19 HB56U232BA/SBA Series Physical Outline Unit: mm inch Front side 107.95 4.25 101.19 3.98 1 72 1.27 typ. 0.05 2.03 0.08 6.35 0.25 6.35 0.25 44.45 1.75 44.45 1.75 R1.57 R0.062 Back side 1 72 Deteil A 2.54 min 0.10 1.04 0.03 0.041 0.001 20 2.54 min. 0.10 A 0.25 max 0.01 ,, ,, ,, ,, ,, ,, ,, + 0.10 1.27 - 0.08 + 0.004 0.05 - 0.003 3.17 min 0.125 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 10.16 0.40 25.40 1.00 3.175 0.125 R1.57 R0.062 6.35 0.25 2-O 5.28 max 0.208 HB56U232BA/SBA Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright (c) Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 21 HB56U232BA/SBA Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 1.0 Feb. 20, 1997 Initial issue S. Tsukui K. Tsuneda 2.0 May. 26, 1997 (referred to HM5117805 rev. 3.0) Correct errors 22